The present invention relates generally to integrated circuits and fabrication inspection techniques. More particularly, the present invention relates to integrated circuits and fabrication techniques that facilitate the measurement of source/drain junction overlap and channel length in MOS transistors.
In the semiconductor industry, device sizes are becoming smaller and smaller. Performance of devices, such as transistors that are fabricated in an integrated circuit, strongly depend on the precision of manufacturing small features which form the transistor, as well as the characterization of the various features.
In the field of metal-oxide-silicon (MOS) transistors, advances in manufacturing and integration techniques of metal-oxide-silicon field effect transistors (MOSFETs) have allowed for devices having a gate length of substantially less than 0.5 microns. As the gate length decreases, however, various parasitic effects can have a significant impact on the performance of the device. Furthermore, as technology continues to provide for smaller and smaller gate lengths, a physical gate length (i.e., metallurgical length of the gate from junction to junction) fails to directly correlate with an effective electrical channel length (i.e., an electrical parameter which can be used to accurately define the performance of the device).
One method of determining the electrical channel length in the prior art has been to use a capacitance-voltage (C-V) method, wherein a voltage is applied to the drain of the transistor and the resulting capacitance in the channel region is measured to determine the effective electrical channel length of the transistor. This method, however, tends to fail when the gate length of the transistor is decreased below 0.5 microns. Failure of the C-V method to accurately determine the channel length is due, at least in part, to the relative capacitance of a source/drain junction overlap of the transistor. A length of the source/drain junction overlap remains generally constant, independent of gate length, and therefore the source/drain junction overlap plays a greater role in the measured capacitance in the C-V method as the gate length decreases. The source/drain junction overlap of a small transistor having a gate length of less than 0.5 microns can therefore have a detrimental effect on the determination of the electrical channel length using the C-V method.
Another method of determining the gate length and effective channel length of a transistor in the prior art has been to use a current-voltage (I-V) method, wherein a drain voltage is applied to the transistor and the resulting current between the drain and the source is measured. This method, however, requires that a source/drain junction overlap width be known prior to the determination of the gate length. Typically, the source/drain junction overlap width is ascertained from empirical data, such as through the use of scanning electron microscopy (SEM). Utilizing SEM to measure the source/drain junction overlap width, however, is typically destructive to the device, and furthermore cannot typically be performed in-situ.
Therefore, a method of determining the source/drain junction overlap and the channel length of devices such as MOS transistors is needed, wherein an accurate effective electrical channel length and source/drain junction overlap length can be determined in-situ in a non-destructive manner.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to a method for determining a junction overlap and a channel length of a small device such as a MOS transistor formed on a semiconductor substrate. The method comprises utilizing a large reference device formed on the substrate, the reference device having a source, a drain, and a gate, wherein a channel is defined between the source and the drain of the reference device. In accordance with one exemplary aspect of the present invention, the length of the channel of the reference device is known, and the source, drain, and substrate are grounded. A predetermined gate voltage is applied to the gate of the reference device, and a gate to channel current is measured.
The small device also comprises a source, a drain, and a gate, and a channel is furthermore defined between the source and the drain of the small device. In accordance with another aspect of the present invention, the source, drain, and substrate are grounded, and a predetermined gate voltage is applied to the gate of the small device. A gate to channel current is also measured for the small device.
The substrate and one of the source or the drain of the small device are floated, and a predetermined drain voltage is applied to the source or the drain which is not floating. Consequently, the current between the respective source or the drain which is not floating and the gate is measured. According to yet another exemplary aspect of the invention, a source/drain junction overlap length is calculated by multiplying the known channel length of the reference device by the measured current between the gate and the respective source or drain of the small device, and dividing by the measured current between the gate and the channel of the reference device.
In accordance with still another exemplary aspect of the present invention, the channel length of the small device is determined by multiplying the known channel length of the reference device by the measured current between the gate and the channel of the small device, dividing by the measured current between the gate and the channel of the large device, and then subtracting twice the calculated overlap.